In many advanced applications, Digital Signal Processing (DSP) is required, usually when analog and digital systems meet. Increasing the number of operands being used in each calculation increases the data computation rate. Thus, the standard 2-input Adder can add two operands while the 3-input Adder can add three operands, increasing the data computation rate by a factor of 50%.
One of the main tasks of DSP is the summation of multiplication operations:ΣAi*Xi
In order to execute such tasks a Multiply and Accumulate (MAC) Unit is used, which also requires a multiplier and adder. The trend in DSP implementation is to increase the number of MAC Units in order to increase the data computation rate. The 3-input AU can be used in such cases and has several advantages.
In the case where the products of two multipliers should be summed, the 3-input arithmetic unit illustrated in FIG. 1b can accumulate the result more easily than two separate 2-input Adders illustrated in FIG. 1a, thus requiring only one accumulator instead of two.
In other applications such as complex multiplication, the 3-input AU can increase data computation rates. Complex multiplication is very important and is used in many applications such as FFT (Fast Fourier Transform), which is very commonly used in many DSP applications. The multiplication of two complex numbers A and B is computed as follows:Σ(Ar+i*Ai)*(Br+i*Bi)=Σ[(Ar*Br−Ai*Bi)+i*(Ar*Bi+Ai*Br)]
In order to implement such a task, the real and imaginary parts have to be calculated separately. In each calculation, two multipliers are needed as well as a single 3-input AU in order to accumulate the multipliers result, as shown in FIG. 1a. 
As is known, when an adder is used to subtract a second operand from a first operand, this is done by adding to the first operand the twos complement of the second operand. This, in turn, is achieved by inverting each bit in the second operand and adding “1”, thus, in effect, requiring an additional adder, and increasing the computation time because each adder imposes its own computing overhead. The problem is further compounded when second and third operands are successively subtracted from a first operand, i.e. A−B−C. In this case, the two complements of both B and C must be derived by inverting each operand and adding two “1”s, thus requiring in total five adders, and even further increasing the computation overhead.
It would therefore be of particular benefit to provide a 3-input adder for inputting three operands A, B and C and being capable of computing A−B−C without requiring additional adder stages, since this would decrease the computing overhead and increase computation speed.
It would be of further benefit to configure such a 3-input adder to implement split operand arithmetic so as more efficiently to carry out complex arithmetic, as explained above.